Jobs at X-FAB

The X-FAB Group - about 4,000 employees - is the leading analog/mixed-signal foundry manufacturing silicon wafers for analog-digital integrated circuits (mixed-signal ICs). X-FAB customers benefit from high-performance technologies, excellent technical design and prototyping services; and fast, easy and flexible foundry access worldwide.

Senior Engineer Design Support (m/f/d) Focus Memory Development

Erfurt, Germany

Our Benefits:

There are many good reasons to be a part of our #xfabulous family!

  • You are an important part of the large international team and benefit from it!
  • Attractive & transparent salary system according to company tariff.
  • We share our success with you and pay a bonus when we reach our goals.
  • Professional, financial and personal development
  • Work-life balance: we offer you up to 2 days full salary if your child is sick.
  • With free parking you can start your work relaxed.
  • Due to our excellent connections, you can get to us on time by tram or car without the typical city traffic.
  • Employees recruit employees - Do you know someone who would also fits with us? Then you will receive a bonus through our employee referral program.
  • We strengthen our spirit as an X-FABulous family with our company events.
  • Free drinks every day


Your role:

At our Erfurt site, we are looking for a Senior Engineer Design Support (m/f/d) with a focus on Memory Development in the Digital IP department to contribute to a highly innovative team by designing and developing high quality SRAM and ROM. You will work with other team members on the new process design challenges. You will have the chance to create novel low power and high-performance circuits and develop in-house design and verification flows for SRAM and ROM design in the context of ISO26262.

  • Architecture definition and schematic design of RAM and ROM compilers to get the most optimal circuit in terms of power and performance.
  • Verification of leafcells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
  • Implement memory characterization flows based on NLDM/NLPM and CCS characterization
  • Mitigate risks through proactive design analysis
  • Generate front-end views (LIB) for memory IP integration in System-on-Chip.
  • Documentation and design review organization for compliant development in the context of ISO26262
  • Development QA flow for design verification including EMIR analysis
  • Direct design support to customers, analysis of customer designs, deriving proposals
    • Performing analysis and proposing solutions to technical problems
    • Handling customer queries in case of failures and problems


Your profile:

  • Qualification: Master or higher in Electronics Engineering
  • 5 years of working experience in circuit block design with good overview of the full design cycle (knowledge of industry standard circuit simulation and design tools).
  • Good understanding of semiconductor process technologies and device physics.
  • Solid knowledge of generating power/current consumption/margin data of circuit blocks, as well as validation of data and QA process
  • Very good written and spoken English skills


We are looking forward to hearing from you!

Contact person : Katharina Fietzsch

Apply now

Your benefits of applying without a profile:
  • Easy application without any registration
  • Only contact details and CV are required and voluntary attachment upload
  • Takes only 3 minutes


Apply without profile
Your benefits of creating a profile:
  • Create your convincing applicant profile
  • Track your application status regularly
  • Save your application and continue at any time
  • Takes only 10 minutes


Apply with profile