Digital Design Engineer (f/m/x)
Corbeil-Essonnes, France
Responsibilities
You will be part of a team responsible in digital IP development including RAM, ROM and digital libraries. You will have the responsibility to specify and design digital Integrated Circuit embedding the developed digital IPs to allow their Silicon validation.
Your Tasks
Specifications of test chips allowing the silicon measurement of all parameters of RAM, ROM and digital libraries e.g., leakage current, power consumption, access time, peak current, … Propose design solution allowing the most accurate measurements.
Develop digital Integrated Circuit including the full development flow RTL, Synthesis, DFT insertion, Place and Route, Physical Verification (DRC, LVS), RTL and gate level Simulation.
Generate functional Test patterns e.g., ATPG and custom test patterns. Define by simulation limits for parametric tests with Static Timing Analysis reports, Power Analysis reports
Evaluate new DFT methodology e.g., Cell-Aware Test patterns
Documentation relative to IC datasheet and test datasheet
Interface with Test Engineers, organize debug session for issue analysis
Contribute to QA flow for digital IP usage. Interface with digital IP designers. Report and document improvement for better digital IP integration/usage.
Specify and design Test Qualification Vehicle for digital IP and technology process qualification and demonstrator to highlight the capability of the technology and digital IP portfolio.
Any other assignment and role deemed appropriated might be assigned to you from time to time
Your Profile
- Master or higher in Electronics Engineering.
- Minimum 5 years of working experience in developing digital Integrated Circuit. Mandatory Back-End digital design skills (Place and Route, Physical Verification). Front-End digital design (RTL) is an advantage.
- Good communication skills – good level in English, written and spoken.
- Teamwork and collaboration skills, working within multi-national, multi-site team
- Open, curious in new design implementation, new DFT methodology, integrity and friendly when engaging internal/external customers.
- Good knowledge and understanding of digital circuits
- Experience with Place and Route tool for floor planning, CTS and routing and Physical Verification (LVS, DRC)
- Scripting (TCL, perl, python) for automatization
Contact person : Mathieu Quenard
- Easy application without any registration
- Only contact details and CV are required and voluntary attachment upload
- Takes only 3 minutes
- Create your convincing applicant profile
- Track your application status regularly
- Save your application and continue at any time
- Takes only 10 minutes